1. Field of the Invention
The present invention relates to a static random access memory and a method for fabricating a semiconductor structure, and more particularly, to a static random access memory with a high-k dielectric layer and a method for fabricating a semiconductor structure with a high-K dielectric layer.
2. Description of the Prior Art
In a traditional semiconductor process, silicon dioxide is usually used to form a gate dielectric layer. However, with rapid development in the integrated circuit industry, to increase the integrity and driving capacity of elements, the whole circuit element must be designed with reduced profile. As line width of the gate is narrowed, the thickness of the gate dielectric layer must also be reduced. This may increase the possibility of direct tunneling, which may result in sudden increase of the gate leakage current.
To address this issue, dielectric layer with high-k becomes attractive for being used as the gate dielectric layer material. However, currently, there are still technical difficulties in incorporating the high-k dielectric layer into the transistor. This is because the use of high-k dielectric material may reduce the migration rate and element reliability. In addition, as the gate dielectric layer is getting thinner, Boron penetration and poly depletion become more serious. The Boron penetration can be mitigated by doping a tiny amount of nitrogen into the oxide, but the ploy depletion cannot be avoided. Further, since the use of the high-k dielectric layer may increase the threshold voltage of the element, the high-k dielectric layer and the polysilicon gate cannot be integrated together. Accordingly, it is proposed to replace the polysilicon with metal gate, which facilitates avoiding the poly depletion as well as reducing the gate paresitic resistance.
However, in conventional methods of forming a typical gate structure having the high-k dielectric layer and metal gate, the dummy polysilicon gate is removed after it is formed on the high-k dielectric layer, and a metal gate is formed later. This may cause the high-k dielectric layer to be damaged during the course of removing the dummy polysilicon gate, which would degrade its original property of high resistance.
Moreover, integrating the fabrication process of these elements having high-k dielectric layer and fabrication process of other elements on a chip may cause many problems on various elements. For example, the earlier formed high-k dielectric layer and metal gate will be subjected to multiple high temperature thermal processes, which may change the original properties of these layers. For example, this may degrade the quality of the interface between the high-k dielectric layer and the metal gate, which may easily, especially in a P-type transistor, cause roll-off of a threshold voltage of the transistor, reducing the element reliability. Another problem may be that an extra high-k dielectric layer is formed at the PN interface of the static random access memory, which significantly reduces the performance of the static random access memory.